Modern high performance synchronous computer systems typically require two clock signals to create timing signals for enabling various state devices within the computer. One of the clock signals (Master) operates at a higher frequency than the other clock signal (Ref), with the Master clock signal shaping the timing signals or sub-phases of the Ref clock signal. In order to create the sub-phase timing signals, it is necessary that the Master and Ref clock signals be aligned or synchronized. However, skew and propagation delays can complicate such synchronization.
Skew, which can be defined as the settling of voltage levels to final values at different times due to differences in the electrical characteristics of state devices and transmission lines, can cause timing errors since the Master and Ref clock signals which are transmitted close together but in a defined sequence, may arrive in an unpredictable sequence at a state device. As a result, there is a need to change certain characteristics of the transmission line used for propagation of the clock signals to synchronize the signals and compensate for the potential range of skew present in the computer system.
A clock signal propagates as a wave from a transmitter to a receiver or state device along a transmission line. The time necessary for the wave to travel along the line is called the propagation time (t.sub.pd). The propagation speed (v.sub.p) of the wave/signal can be expressed in terms of the distance (d) traveled by the signal divided by the propagation time t.sub.pd : EQU v.sub.p =(d/t.sub.pd)
The propagation speed v.sub.p is a physical property of the transmission line and may be indicated in the form of a propagation delay (t.sub.d), which is the inverse of the propagation speed v.sub.p. The propagation delay t.sub.d of a transmission line can be simply expressed in terms of the inductive and capacitive elements of the line: EQU t.sub.d =sqrt (L*C)
Attempts to change the propagation characteristics of transmission lines have resulted in changing the delay characteristics of the line. Conventional delay line technology, or more specifically delay line circuits, typically resemble a lumped model, otherwise known as a ladder network. The ladder network may consist of fixed lumped elements such as inductors, capacitors, and resistors whose values cannot be dynamically altered to compensate for the required range of delay. Other topologies, for example lattice networks, are entirely differential in nature and require transformer coupling which is expensive and often band-limiting. Most of the circuit elements used in the lumped design have parasitic losses or resonances, thereby precluding their use over certain frequency ranges.
Changes to either the capacitive or inductive elements of a transmission line will therefore alter the line's delay characteristics. In order to compensate for the potential range of skew present in the computer system, there is the need to dynamically vary the capacitance or inductance of the line. But, changes to the inductance or capacitance will, in turn, cause a change in the characteristic impedance of the transmission line.
The ratio of voltage to current in a clock signal traveling along a transmission line is called the characteristic impedance Z.sub.o of the line. The characteristic impedance Z.sub.o is also a physical property of the transmission line, that is, it depends upon the line's dielectric properties and capacitive load and, as such, can be expressed in terms of the inductive and capacitive elements of the line: EQU Z.sub.o =sqrt (L/C)
Conventional delay lines are typically low-pass filter circuits configured as ladder networks. These networks are typically terminated with matching resistances at the ends of the delay line. In other words, the line is terminated by a matched pair of resistances whose value is approximately equal to the characteristic impedance of the line, so that signals reaching the end of the line are absorbed, thereby reducing reflections. Proper termination of the transmission line also minimizes variations in insertion loss of the line or, in other words, maintains a constant amplitude level of the signals. As the characteristic impedance Z.sub.o of the conventional delay line varies, a mismatch with the termination resistance of the line is likely, resulting in reflections of the signals propagating the line which could cause the false triggering of state devices.
Therefore, in accordance with an aspect of the present invention, a feature is to provide a range of variable insertion delay over a wide band of high frequencies in order to synchronize two clock signals originating from signal paths that have unknown and differing skew.
Additionally, a feature of the present invention is to provide a low-cost variable delay line configuration having electronically adjustable delay that exhibits broad bandwidth and stable insertion loss characteristics.
In accordance with another aspect of the invention, a feature is to provide an improved termination technique for a variable delay line that utilizes a pair of impedance optimizing resistances, resulting in improved insertion loss stability and a multi-decade bandwidth characteristic over a frequency range of kilohertz to gigahertz.
A further feature of the present invention is to provide an electronically variable delay line that utilizes components which are less expensive than available vendor supplied devices which do not have the broad frequency range and other characteristics exhibited by this invention.